The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, more specifically a semiconductor device having high withstand voltage transistors and a method for fabricating the semiconductor device.
In organic EL panels, LCD drivers, ink jet printers, etc., it is noted to mount logic transistors, and high withstand voltage transistors mixedly on and the same substrate for the purpose of their general high operational speed.
A proposed semiconductor device having logic transistors, and high withstand voltage transistors mixed mounted will be explained with reference to FIG. 16. FIG. 16 is a sectional view of the proposed semiconductor device. In FIG. 16, a logic region shown on the left side of the drawing, and a high withstand voltage region is shown on the right side of the drawing.
Element isolation regions 214 for defining element regions 212a, 212b are formed on the surface of a semiconductor substrate 210. In the element region 212a of the logic region 216 a transistor 220 of relatively low withstand voltage having a gate electrode 226, a source region 236a and a drain region 236b is formed. The source region 236a has a lightly doped source region 230a and a heavily doped source region 234a. The drain region 236b has a lightly doped drain region 230b and a heavily doped drain region 234b. On the other hand, in the source region 212b of the high withstand voltage region 218 a relatively high withstand voltage transistor 222 having a gate electrode 226, a source region 245a and a drain region 245b is formed. The source region 245a has a lightly doped source region 242a and a heavily doped source region 244a. The drain region 245b has a lightly doped drain region 242b and a heavily doped drain region 244b. An inter-layer insulation film 250 is formed on the semiconductor substrate 210 with the transistors 220, 222 formed on. Conductor plugs 254 are formed in the inter-layer insulation film 250 respectively down to the source regions 236a, 245a and the drain regions 236a, 245b. An interconnection is formed on the inter-layer insulation film 250, connected to the conductor plugs 254.
The proposed semiconductor device, in which the logic transistors 220, and the high withstand voltage transistors 222 are formed mixedly on one and the same substrate, can contribute to higher operation speed of electronic devices.
Recently, semiconductor devices are increasingly micronized. However, simply micronizing a semiconductor device causes increase a contact resistance and a sheet resistance in the source/drain. As a countermeasure to this, in a logic transistor whose gate length is below, e.g., 0.35 μm, usually a silicide layer is formed on the source/drain region for the purpose of depressing the contact resistance and the sheet resistance in the source/drain.
Another proposed semiconductor device which has the silicide layer formed on the source/drain region will be explained with reference to FIG. 17. FIG. 17 is a sectional view of another proposed semiconductor device.
As shown in FIG. 17, the silicide layer 240 is formed respectively on the heavily doped source regions 234a, 244a and the heavily-doped drain regions 234b, 244b. 
Said another proposed semiconductor device shown in FIG. 17, in which the silicide layer 240 is formed on the source/drain regions, can be micronized while the contact resistance and the sheet resistance in the source/drain are depressed low.
Patent Reference 1 also discloses a semiconductor device having a silicide layer formed on the source/drain regions.
Following references disclose the background art of the present invention.
[Patent Reference 1]
Specification of Japanese Patent Application Unexamined Publication No. Hei 11-126900
[Patent Reference 2]
Specification of Japanese Patent Application Unexamined Publication No. Hei 9-260590
However, the proposed semiconductor device shown in FIG. 16 cannot ensure sufficient withstand voltage of the high withstand voltage transistors. The semiconductor device proposed in Patent Reference 1 cannot ensure sufficiently high withstand voltage.
Here, it can be proposed that a silicide layer is formed on the source/drain diffused layer of the logic transistors only, and in the high withstand voltage transistor, the silicide layer is not formed, but an insulation film covers the source/drain diffused layer thereof. In this case, however, it is difficult to obtain good contact in the high withstand voltage transistor, and the contact resistance and the sheet resistance in the high withstand voltage transistor are very high.